1. Field of the Invention
Embodiments of the present invention relate to an array substrate for a display device and a manufacturing method thereof. More particularly, the embodiments of the present invention relate to an array substrate for a display device and a manufacturing method thereof, which can prevent problems due to the damage of a passivation layer in a passivation hole area formed on a Source/Drain (S/D) metal pattern in a non-active area.
2. Description of the Related Art
With the progress of an information-oriented society, demands for display devices for displaying images have increased in various forms. Recently, various display devices, such as a Liquid Crystal Display (LCD), a Plasma Display Panel (PDP), and an Organic Light Emitting Diode Display (OLED) device, have been utilized.
Among these display devices, a Liquid Crystal Display (LCD) device typically includes an array substrate including a Thin Film Transistor (TFT), which is a switching element for controlling on/off of each pixel area; an upper substrate including a color filter and/or a black matrix, etc.; a display panel including a liquid crystal material layer formed between the array substrate and the upper substrate; and a driving unit for controlling the TFT. In such an LCD device, an alignment state of the liquid crystal layer is controlled according to an electric field applied between a pixel (PXL) electrode and a common voltage (Vcom) electrode provided in a pixel area, and thereby the transmittance of light is adjusted to allow an image to be displayed.
In the array substrate, an Active Area (AA) and a Non-active Area (NA) may be defined. The Active Area includes one or more pixels which display an image. Multiple gate lines GL and multiple data lines DL intersect to define Pixels (P) on an inner surface of the active area of the array substrate, which is typically referred to as a “lower substrate,” and each of the intersections between the gate lines and the data lines may be provided with a TFT that is respectively connected on a one-to-one ratio to a transparent pixel electrode formed in each pixel P.
On the array substrate, multiple layers, such as a gate metal layer, a semiconductor layer, a source/drain metal layer, a pixel electrode layer, a common electrode layer, and the like, may be formed in order to form the TFTs and the wire lines, and an inter-layer insulating layer for insulation between layers or a protection layer for protecting each layer may be formed.
There is also a Twisted Nematic (TN) mode, in which an array substrate having a pixel electrode formed thereon and an upper substrate having a common voltage electrode formed thereon are separated from each other, a liquid crystal material is injected between the array substrate and the upper substrate, and liquid crystal molecules in a nematic phase are driven in a direction vertical to the substrates. However, an LCD device of the above-described TN mode may be disadvantageous due to its narrow viewing angle of about 90 degrees.
In contrast, there is an LCD device of functioning in an In-Plane Switching (IPS) mode, where liquid crystal molecules may be driven in a direction horizontal to the substrates, thereby improving a viewing angle by more than 170 degrees. The LCD devices using IPS mode (in which, basically, a pixel electrode and a common voltage electrode may be simultaneously formed on a lower substrate or an array substrate) may be divided into a type in which both the pixel electrode and the common voltage electrode are formed in an identical layer, and a Fringe Field Switching (FFS) type in which both electrodes are formed spaced apart from each other in a horizontal direction in a state of interposing one or more insulating layers, and where one electrode has a finger shape.
Further, a connection pad for connection to a driving unit disposed at an inner or outer portion of the array substrate, a signal application pad for applying a reference voltage or reference signals, various pads for measurement, and the like, may be formed on a part of the non-active area outside the active area in the array substrate.
In the non-active area, multiple passivation holes or multiple passivation contact holes may be formed by opening parts of an insulating layer or a passivation layer located on an S/D metal layer laminated on the array substrate.
The passivation hole may be an aperture that exposes an S/D metal pattern due to the removal of a part of a passivation layer or an insulating layer laminated on an S/D metal pattern. In order to protect the exposed S/D metal pattern, another additional passivation layer may be formed on the passivation hole.
In the case of the passivation hole formed on the S/D metal pattern as described above, adhesion strength is weakened between the S/D metal pattern layer in a passivation hole area and the additional passivation layer, which is laminated on the S/D metal pattern layer so as to contact the S/D metal pattern layer. Thus, a delamination phenomenon may occur between both contact layers. Further, a foreign material peel-off phenomenon, in which a part of an upper passivation layer is peeled off, may occur during an additional process.
When the delamination phenomenon occurs between the S/D metal layer and the additional passivation layer located on the S/D metal layer in the passivation hole area, the accuracy of measurement may be reduced. For example, when the foreign material generated from the passivation layer by the foreign material peel-off phenomenon enters the active area and is fixed to the active area, display failures such as a pixel defect or a hot pixel (or the like) may occur.